We are seeking a Principal SOC Design Lead to support SOC development for our next generation, mixed signal, wireless products. The role will include “hands-on” direction of our Silicon Development Team in the areas of RTL design, design verification, synthesis, STA, floor planning, and power analysis using an industry leading ASIC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments.
· Candidate will provide hands on technical leadership to the WSG Silicon Development Team in the creation of digital IP and mixed signal subsystems.
· Candidate will lead the integration of subsystems into a MIPS processor based SOC
· Work with architecture and applications teams to ensure target specifications and customer requirements are achieved.
· Work with the design team in overcoming HDL design challenges, achieving verification goals, and assisting with critical debug activities at both the unit and full-chip level
· Validate and debug silicon products in support of release to production.
· Direct spec reviews, code reviews, coverage analysis, etc. in support of corporate ISO Quality Systems
· Interface with and support applications, product and test engineering, marketing, development systems, technology development, CAD, layout and other design organizations
· Expertise in RTL coding using Verilog/SystemVerilog
· Knowledgeable in Chip level Design and Integration activities
· Hands on Experience with C Programming Language
· Proficiency in common UNIX scripting languages (Perl, Python, csh, etc.)
· Excellent debug skills in both functional and gate level simulations
· Good Knowledge of SOC peripherals like ADC/Timers/ECAN/USB/Ethernet
· Knowledge of revision control tools such as CVS, Perforce, DesignSync
· Working knowledge of semiconductor device physics, transistor characteristics, and associated layout considerations
· Superior Written and Verbal Communication skills
· Extensive experience working with cross functional global teams
· Clear history of proactive leadership
· Experience with MIPS processor based subsystem
· Experience with Verification Methodologies such as UVM/VMM
· Knowledge of Programming Languages such as C++ or System C
· Experience with synthesis and static timing tools
· Knowledge and exposure to complete SOC RTL to GDS to silicon release flow is desired
· Experience working on WiFi, WLAN, or Bluetooth products
BS or MS in Electrical/Electronic Engineering with 10+ years experience, MSEE preferred