Engineer - Digital Design - RTL Design - Mixed Sig Job in Mountain View California (CA)

Engineer - Digital Design - RTL Design - Mixed Signal - Verilog Engineer - Digital Design - RTL Design - Mixed Signal - Verilog - C - Matlab - FPGA - ASIC - Perl - Skills Required - Engineer, Mixed-Signal Products, RTL Design, Module Level Architecture, RTL Code Verification, Verilog, 'C', Matlab, FPGA ASIC Design Environments, Digital/Mixed-Signal IC Design

Engineer - Digital Design - RTL Design - Mixed Signal Products - Verilog - C - Matlab - FPGA - ASIC - Perl - Unix Shell - IC Design - Digital PLL - AES - Encryption - System Level Modeling/Simulation - Gate Level - Verification - Debug - Electrical Engineering - Micro-Architecture - Lab Environment

Are you a Digital Design Engineer looking for a better opportunity? Do you have at least 5-years industry experience in digital/mixed-signal IC design at 0.25 µm or smaller technology, with clock frequency >200 MHz, and a PhD* in Electrical Engineering or closely related field? If so. Read On!

(*Note: Will consider MSEE with 7+ years, or a BSEE with 9+ years, experience as stated above.)

We have a Digital Design Engineer position, in the greater Mountain View vicinity, with an early stage, entrepreneurial technology-oriented organization, recognized as a pioneer of ultra reliable, utility scale, inverter-less solar power systems.

In this role, you'll report to the VP of Engineering and have responsibility for defining module level architecture specifications for next generation Mixed-Signal products. You'll also be responsible for RTL code implementation using Verilog/C/Matlab and own pre-layout synthesis and timing closure using FPGA/ASIC design environment.

Some of the other things you'll be doing include:

* Work on post-layout timing closure
* Work to debug test cases in a RTL and Gate Level simulation environment
* Define and generate assertion for your own module
* Post-silicon debug and correlation.

What you need for this position:

BSEE, MSEE, or PhD with a minimum of at least 9, 7 or 5 years of experience, respectively, in digital/mixed-signal IC design at 0.25 µm or smaller technology with clock frequency > 200 MHz
* Experience of entire design cycle from micro-architecture specification definition, Verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment
* Start-up company experience or comparable experience working within a new business entity within a larger corporation is essential
* Strong language user in Verilog, Perl and Unix Shell
* Experience in both RTL and gate level verification and debug
* Experience in coverage based/random test environment and assertion generation
* Experience in FPGA and ASIC design environments
* Some experience in system level modeling/simulation
* Some experience in custom logic design (at the structural level)

A big plus:

* Design experience in many of the following product areas:
-Microprogrammed core design
-Encryption, key management, AES
-High speed serial link
-High speed arithmetic, transcendent functions
-Some experience with digital filters, correlators
-Digital PLL

What's in it for you:

* Excellent compensation and benefits. including stock options
* Excellent growth opportunity
* Opportunity to be a part of a fast-paced, early stage, entrepreneurial technology-oriented company, positioned to become a leader in the renewable energy industry.

So, if your Digital Design Engineer looking for a better opportunity, and you have the appropriate combination of degree and respective years of experience in digital/mixed-signal IC design at 0.25 µm or smaller technology with clock frequency > 200 MHz, plus meet all the additional requirements listed above. Please Apply Today!

Note: Only local candidates will be considered at this time, and there is no H1 sponsorship available for this position. - JT-DigitalDesEng-CA - , , , , , CyberCoders CyberScientific